1. Field of the Invention
The present invention generally relates to programmable logic devices, and more particularly, to a programmable logic device having logic elements with dedicated hardware to programmably configure Look Up Tables (LUTs) as registers.
2. Description of Related Art
A Programmable Logic Device (PLD) is a semiconductor integrated circuit that contains fixed logic circuitry that can be programmed to perform a host of logic functions. In the semiconductor industry, PLDs are becoming increasingly popular for a number of reasons. Due to the advances of chip manufacturing technology, application specific integrated circuits (ASICs) designs have become incredibly complex. This complexity not only adds to design costs, but also the duration of time needed to develop an application specific design. To compound this problem, product life cycles are shrinking rapidly. As a result, it is often not feasible for original equipment manufacturers (OEMs) to design and use ASICs. OEMs are therefore relying more and more on PLDs. The same advances in fabrication technology have also resulted in PLDs with improved density and speed performance. Sophisticated programming software enables complex logic functions to be rapidly developed for PLDs. Furthermore, logic designs generally can also be easily migrated from one generation of PLDs to the next, further reducing product development times. The closing of the price-performance gap with ASICs and reduced product development times makes the use of PLDs compelling for many OEMs.
Most PLDs contain a two-dimensional row and column based architecture to implement custom logic. A series of row and column interconnects, typically of varying length and speed, provide signal and clock interconnects between blocks of logic on the PLD. The blocks of logic, often referred to by such names as Logic Elements (LE5), Adaptive Logic Modules (ALMs), or Complex Logic Blocks (CLBs), usually include one or more look up table (LUTs), registers for generating registered logic outputs, adders and other circuitry to implement various logic and arithmetic functions.
With many logic designs implemented on PLDs, it would be desirable to provide logic elements having additional registers for handling functions beyond just generating registered logic outputs. This is particularly true with the advances in semiconductor process technology. As device geometries shrink with each new generation of process technology, the propagation delays of logic devices (e.g., LUTs and registers) and signal propagation delays over interconnect are also reduced. However, the reduction in the propagation delays between logic devices and interconnect is not symmetrical. In general, interconnect propagation delays have not been reduced at the same rate as propagation delays through logic. As a consequence, designers have added more registers in the signal propagation paths of circuit designs for the purpose of pipelining the critical path of the circuit, which is defined as the longest possible delay between any two registers (i.e., typically an input and an output register). By adding extra registers, the clock rate used to clock the operations of the circuit can be increased. In other words, by adding more pipelined stages to the critical path, and increasing the clock speed, the net result is a faster throughput.
With existing PLD architectures, such as those mentioned above, the registers in a logic element can be used for pipelining. When the registers are used for this function though, the remaining logic of the logic element remains un-used. In other words, the other logic elements, such as the LUTs, can not be used for implementing logic. While it is possible for circuit designers to implement LUTs in a logic element as a register with existing PLDs, to do so is impractical. With current PLDs, no local interconnect or other hardware resources within the logic element is provided for implementing LUTs as a register. Instead, signals generated by one LUT in a logic element need to be routed through the general interconnect of the device and then back into a second LUT in the logic element to implement the register function. Since the signals are routed over the general interconnect, the operational speed of the LUTs when configured as a register is far too slow to be practically used in most design implementations, such as pipelining. Thus, when the registers of a logic element are used for pipelining, the LUT(s) of a logic element are essentially wasted. Accordingly, while circuit designers may currently use the registers in logic elements for pipelining to increase clock speeds and throughput, the tradeoff is often an inefficient use of the LUT resources on the device.
A PLD architecture having logic elements with dedicated hardware to configure the LUTs of a logic element to either perform logic functions or to operate as a register for pipelining or other purposes is therefore needed.